1. Field of the Invention
The present invention relates to MOS transistors and, more particularly, to a MOS transistor and a method of forming the MOS transistor with a SiON etch stop layer that protects the transistor from plasma induced damage (PID) and hot carrier degradation.
2. Description of the Related Art
A MOS transistor is a semiconductor device that can be fabricated in many well known ways. In one prior art approach, an etch stop layer of silicon oxynitride (SiON) is formed over the device after the source and drain regions and the gate of the device have been silicided. In this approach, the SiON etch stop layer performs two important functions.
First, the SiON layer provides a conductive path to ground that prevents plasma induced damage (PID). PID results when plasma etching is used, and can lead to the build up of a charge on the transistor gate that, if not discharged, can seriously damage or destroy the underlying gate oxide layer. Second, when the contact openings are subsequently formed, the SiON etch stop layer eliminates harmful over-etching of the silicided layers that can be caused by variations in the thickness of an overlying layer of dielectric material.
FIGS. 1A-1D show a series of cross-sectional views that illustrate a prior-art method 100 of fabricating a MOS transistor with a SiON etch stop layer. As shown in FIG. 1A, method 100 utilizes a conventionally-formed MOS device 110 that includes a semiconductor material 112 of a first conductivity type, and spaced-apart source and drain regions 114 and 116 of a second conductivity type that are formed in semiconductor material 112.
MOS device 110 also includes a channel region 118 that lies between the source and drain regions 114 and 116, a gate oxide layer 120 that lies over channel region 118, and a gate 122 that is formed on gate oxide layer 120 over channel region 118. MOS device 110 further includes a non-conductive side wall spacer 124 that contacts the side walls of gate 122, and metal silicide layers 130, 132, and 134 that are formed on source region 114, drain region 116, and gate 122, respectively.
As further shown in FIG. 1A, method 100 begins by forming a SiON etch stop layer 140 on side wall spacer 124 and metal silicide layers 130, 132, and 134. The TABLE below illustrates two SiON deposition recipes. In the Table, RI(n) is the film's index of refraction, and RI(k) is the film's extinction coefficient.
However, the silane (SiH4) flow rate used during SiON film deposition is critical to controlling the effects of PID. NMOS transistors formed with high SiH4 flow rate levels, such as 115 sccm, have been found to resist plasma charging effects because a high SiH4 flow rate level increases the
TABLELow K SiONHigh K SiONRI (n)2.22.0RI (k)1.021.62Thickness500 Å500 ÅRF Power120 W120 WPressure5.5 Torr5.5 TorrSiH4 Flow54 sccm115 sccmN20 Flow70 sccm70 sccmArgon Flow1900 sccm1900 sccmconductance of the SiON film. On the other hand, NMOS transistors formed with low SiH4 flow rate levels, such as 54 sccm, have been found to be susceptible to plasma charging effects because a low SiH4 flow rate level reduces the conductance of the SiON film.
FIG. 2 shows a prior-art graph that illustrates SiON film conduction versus SiH4 deposition flow rate. As shown in FIG. 2, as the SiH4 deposition flow rate increases from 50 sccm to 120 sccm, the SiON film conductance increases by about three orders of magnitude from approximately 1×10−12 to 1×10−9Ω−1. Thus, when formed at a SiH4 flow rate of 115 sccm, the resulting SiON etch stop layer provides a much more conductive path.
A SiON layer formed at a SiH4 flow rate of 115 sccm is conductive on the order of femto-amps at room temperature and nano-amps at elevated processing temperatures which, although small, is sufficient to provide a grounding path for any plasma induced charge that has built up on gate 122. Thus, in the present example, method 100 utilizes a SiH4 flow rate of 115 sccm. As a result, one advantage of SiON layer 140 is that layer 140 eliminates the possibility of damage that can result from plasma induced charge build up.
Referring again to FIG. 1A, once SiON etch stop layer 140 has been formed, an overlying dielectric layer 142, such as a layer of tetraethylorthosilicate (TEOS), is formed on etch stop layer 140. After overlying dielectric layer 142 has been formed, a mask 144 is formed and patterned on the top surface of dielectric layer 142.
Next, as shown in FIG. 1B, the exposed regions of dielectric layer 142 are etched to form openings 146, 148, and 149. The etch continues until the exposed regions of dielectric layer 142 have been removed from etch stop layer 140 so that openings 146, 148, and 149 expose regions of the top surface of etch stop layer 140.
As a result, dielectric layer 142 can be significantly over-etched to insure that all of exposed dielectric layer 142 has been removed. Thus, another advantage of SiON layer 140 is that at the end of the etch, regardless of any variations in the thickness of dielectric layer 142, which can be significant, the bottoms of openings 146, 148, and 149 lie approximately the same distance from the top surfaces of source region 114, drain region 116, and gate 122, respectively. As a result, method 100 can accommodate contact openings in layer 142 of differing depths.
As shown in FIG. 1C, after openings 146, 148, and 149 have been formed in dielectric layer 142, the exposed regions of SiON etch stop layer 140 are etched away to form openings 150, 152, and 153. In the present example, an etch chemistry is used to remove etch stop layer 140 at a substantially slower rate than dielectric layer 142 was removed.
The etch continues until etch stop layer 140 has been removed to expose regions on the top surfaces of metal silicide layers 130, 132, and 134. After the etch, mask 144 is removed. Once mask 144 has been removed, a metal contact layer is deposited on dielectric layer 142 to fill up openings 150, 152, and 153. Following the deposition of the metal contact layer, the metal contact layer is next planarized until the metal contact layer has been removed from the top surface of dielectric material 142.
As shown in FIG. 1D, the planarization forms a metal source contact 154, a metal drain contact 156, and a metal gate contact 158 in dielectric layer 142 that make electrical connections with source region 114, drain region 116, and gate 122, respectively. After this, method 100 continues with conventional back-end processing steps to complete the formation of a MOS transistor.
One problem with method 100 when using a SiH4 flow rate of 115 sccm during the formation of SiON etch stop layer 140 is that the resulting MOS transistor is more susceptible to hot carrier injection. This, in turn, accelerates the hot carrier degradation of the transistor. Hot carrier injection causes device parameters, such as the saturation drain current (IDSAT), to degrade with time. Degradation in the IDSAT of a transistor leads to a reduction in digital circuit speed and potential functional failure. The NMOS transistor is particularly prone to hot carrier damage.
FIG. 3 shows a prior-art graph that illustrates the hot carrier degradation of an NMOS transistor fabricated with method 100 when using a SiH4 flow rate of 120 sccm. As shown in FIG. 3, the graph illustrates a measured saturated drain current IDSAT, and an estimated saturated drain current IDES over a number of stress times against IDSAT degradation. (Further, the IDSAT values are measured at VGS=VDS=3.3V, and the device is stressed at VGS stress=1.97V and VDS stress=3.9V.)
As further shown in FIG. 3, for stress times less than 10 ks, the measured saturated drain current IDSAT and the estimated saturated drain current IDES are substantially the same (indicating that the measured saturated drain current IDSAT is degrading with the expected power law dependence).
On the other hand, for stress times between 10 ks and 100 ks, the measured saturated drain current IDSAT improves dramatically when compared to the estimated saturated drain current IDES. However, for stress times greater than 100 ks, the measured saturated drain current IDSAT declines rapidly when compared to the estimated saturated drain current IDES, leading to premature failure. Thus, if failure occurs when degradation reaches 10%, a NMOS transistor formed with a SiH4 flow rate of 120 sccm will fail earlier than predicted due to hot carrier effects.
The increased susceptibility to hot carrier injection is associated with the incorporation of additional hydrogen at the silicon-gate oxide (Si—SiO2) interface during device processing. One source of the addition hydrogen comes from the increased levels of hydrogen that are present when a high SiH4 flow rate level is used in the formation of SiON etch stop layer 140. The Si—H bond, however, is weak (bond strength approximately 0.3 eV), and can be easily broken by hot carrier generated injected electrons.
FIG. 4 shows a prior-art graph that illustrates an example of the hot carrier degradation of an NMOS transistor fabricated with a series of SiH4 flow rate levels. The graph illustrates a series of measured saturated drain currents IDSAT1-IDSAT6 taken from NMOS transistors formed with the series of SiH4 flow rate levels, along with an estimated saturated drain current IDES, taken over a number of stress times against IDSAT degradation. (The IDSAT values are measured at VGS=VDS=3.3V and the device stressed at VGS stress=2.13V, and VDS stress=4.3V.)
As shown in FIG. 4, the series of measured saturated drain currents IDSAT1-IDSAT6 vary based on the flow rate of SiH4 that is used during the formation of SiON etch stop layer 140. In the FIG. 4 example, the series of measured saturated drain currents IDSAT1-IDSAT6 correspond with the series of SiH4 flow rates 50 sccm, 70 sccm, 80 sccm, 90 sccm, 100 sccm, and 120 sccm, respectively.
As further shown in FIG. 4, for the SiH4 flow rate of 50 sccm, the measured saturated drain currents IDSAT1 substantially tracks the estimated saturated drain current IDES. For the SiH4 flow rates of 70-80 sccm, the measured saturated drain currents IDSAT2 and IDSAT3 substantially track the estimated saturated drain current IDES for stress times up to about 7 ks, and then have improved degradation rates for stress times from 7 ks to about 14 ks, and worse degradation rates over 14 ks when compared to the estimated saturated drain current IDES.
However, for the SiH4 flow rates of 90, 100, and 120 sccm, the measured saturated drain currents IDSAT4, IDSAT5, and IDSAT6 track the estimated saturated drain current IDES for stress times of approximately 4 ks, and then have improved degradation rates for stress times from 4 ks to about 11 ks, and worse degradation rates over 11 ks when compared to the estimated saturated drain current IDES. Thus, if failure occurs when degradation reaches 10%, a NMOS transistor formed with a SiH4 flow rate of 90-120 sccm will fail earlier than predicted due to hot carrier effects.
As noted above, however, a 50 sccm SiH4 flow forms a SiON layer that provides very low conductivity. Thus, although a SiH4 flow rate of 50 sccm corresponds with a measured saturated drain current IDSAT1 that substantially tracks the estimated saturated drain current IDES, a SiH4 flow rate of 50 sccm produces a SiON layer which is susceptible to plasma induced charge on gate 122 due to the low conductivity.
One approach to this problem is to select an intermediate SiH4 flow rate. For example, a flow rate of approximately 70-80 sccm produces a SiON film that is one order of magnitude more conductive (approximately 1×10−11Ω−1) which reduces the effects of PID. In addition, SiH4 flow rates of 70 and 80 sccm produce acceptable measured saturated drain currents (e.g., IDSAT2 and IDSAT3) when failure is defined at a degradation of 10%.
However, although SiH4 flow rates of approximately 70-80 sccm provide an improved conductivity when compared to a flow rate of 50 sccm, there is a need for much greater conductivity to fully protect against the effects of PID.